Power efficient technology decomposition and mapping under an extended power consumption model

We propose a new power consumption model which accounts for the power consumption at the internal nodes of a cmos gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the rst step, we generate a nand decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. In the second step, we perform a power e cient technology mapping that nds a minimal power mapping for given timing constraints (subject to the unknown load problem). 1